FPGA Based High Speed SPA Resistant Elliptic Curve Scalar Multiplier Architecture

The higher computational complexity of an elliptic curve scalar point multiplication operation limits its implementation on general purpose processors. Dedicated hardware architectures are essential to reduce the computational time, which results in a substantial increase in the performance of associated cryptographic protocols. This paper presents a unified architecture to compute modular addition, subtraction, and multiplication operations over a finite field of large prime characteristic GF(p). Subsequently, dual instances of the unified architecture are utilized in the design of high speed elliptic curve scalar multiplier architecture. The proposed architecture is synthesized and implemented on several different Xilinx FPGA platforms for different field sizes. The proposed design computes a 192-bit elliptic curve scalar multiplication in 2.3 ms on Virtex-4 FPGA platform. It is 34% faster and requires 40% fewer clock cycles for elliptic curve scalar multiplication and consumes considerable fewer FPGA slices as compared to the other existing designs. The proposed design is also resistant to the timing and simple power analysis (SPA) attacks; therefore it is a good choice in the construction of fast and secure elliptic curve based cryptographic protocols

Speed and Area Optimized Parallel Higher-Radix Modular Multipliers

Modular multiplication is the fundamental and compute-intense operation in many Public-Key crypto-systems. This paper presents two modular multipliers with their efficient architectures based on Booth encoding, higher-radix, and Montgomery powering ladder approaches. Montgomery powering ladder technique enables concurrent execution of main operations in the proposed designs, while higher-radix techniques have been adopted to reduce an iteration count which formally dictates a cycle count. It is also shown that by an adopting Booth encoding logic in the designs helps to reduce their area cost with a slight degradation in the maximum achievable frequencies. The proposed designs are implemented in Verilog HDL and synthesized targeting virtex-6 FPGA platform using Xilinx ISE 14.2 Design suite. The radix-4 multiplier computes a 256-bit modular multiplication in 0.93 ms, occupies 1.6K slices, at 137.87 MHz in a cycle count of n/2+2, whereas the radix-8 multiplier completes the operation in 0.69ms, occupies 3.6K slices, achieves 123.43 MHz frequency in a cycle count of n/3+4. The implementation results reveals that the proposed designs consumes 18% lower FPGA slices without any significant performance degradation as compared to their best contemporary designs

Surgical Outcome of Renal Cell Carcinoma with Tumor Thrombus Extension into Inferior Vena Cava and Right Atrium (Beating Heart Removal of Level 4 Thrombus): A Challenging Scenario

Aim: “To evaluate oncological and surgical outcomes of different levels of tumor thrombus and tumor characteristics secondary to renal cell carcinoma (RCC)”. Materials and Methods: Retrospective review from 2013 to 2020 of 34 patients who underwent radical nephrectomy with thrombectomy for RCC with tumor thrombus extending into the inferior vena cava (IVC) and right atrium (RA) at our center. Level I and most level II tumors were removed using straight forward occluding maneuvers with control of the contralateral renal vein. None of the patients had level III tumor extensions in our study group. For level IV thrombus, a beating heart surgery using a simplified cardiopulmonary bypass (CPB) technique was used for retrieval of thrombus from the right atrium. Results: “Of the 34 patients with thrombus”, 19 patients had level I, 12 patients had level II, none had level III, and three patients had level IV thrombus. Two patients required simplified CPB. Another patient with level IV thrombus CPB, was not attempted in view of refractory hypotension intraoperatively. Pathological evaluation showed clear-cell carcinoma in 67.64%, papillary carcinoma in 17.64%, chromophobe in 5.8%, and squamous cell carcinoma in 8.8% of cases. Left side thrombectomy was difficult surgically, whereas right side thrombectomy did not have any survival advantage. Mean blood loss during the procedure was 325 mL, ranging from 200 to 1000 mL, and mean operative time was 185 min, ranging from 215 to 345 min. The immediate postoperative mortality was 2.9%. Level I thrombus had better survival compared to level II thrombus. Conclusion: Radical nephrectomy with tumor thrombectomy remains the mainstay of treatment in RCC with inferior venacaval extension. The surgical approach and outcome depends on primary tumor size, location, level of thrombus, local invasion of IVC, any hepato-renal dysfunction or any associated comorbidities. The higher the level of thrombus, the greater is the need for prior optimization and the adoption of a multidisciplinary approach for a successful surgical outcome

Hyperoxemia and excess oxygen use in early acute respiratory distress syndrome : Insights from the LUNG SAFE study

Publisher Copyright: © 2020 The Author(s). Copyright: Copyright 2020 Elsevier B.V., All rights reserved.Background: Concerns exist regarding the prevalence and impact of unnecessary oxygen use in patients with acute respiratory distress syndrome (ARDS). We examined this issue in patients with ARDS enrolled in the Large observational study to UNderstand the Global impact of Severe Acute respiratory FailurE (LUNG SAFE) study. Methods: In this secondary analysis of the LUNG SAFE study, we wished to determine the prevalence and the outcomes associated with hyperoxemia on day 1, sustained hyperoxemia, and excessive oxygen use in patients with early ARDS. Patients who fulfilled criteria of ARDS on day 1 and day 2 of acute hypoxemic respiratory failure were categorized based on the presence of hyperoxemia (PaO2 > 100 mmHg) on day 1, sustained (i.e., present on day 1 and day 2) hyperoxemia, or excessive oxygen use (FIO2 ≥ 0.60 during hyperoxemia). Results: Of 2005 patients that met the inclusion criteria, 131 (6.5%) were hypoxemic (PaO2 < 55 mmHg), 607 (30%) had hyperoxemia on day 1, and 250 (12%) had sustained hyperoxemia. Excess FIO2 use occurred in 400 (66%) out of 607 patients with hyperoxemia. Excess FIO2 use decreased from day 1 to day 2 of ARDS, with most hyperoxemic patients on day 2 receiving relatively low FIO2. Multivariate analyses found no independent relationship between day 1 hyperoxemia, sustained hyperoxemia, or excess FIO2 use and adverse clinical outcomes. Mortality was 42% in patients with excess FIO2 use, compared to 39% in a propensity-matched sample of normoxemic (PaO2 55-100 mmHg) patients (P = 0.47). Conclusions: Hyperoxemia and excess oxygen use are both prevalent in early ARDS but are most often non-sustained. No relationship was found between hyperoxemia or excessive oxygen use and patient outcome in this cohort. Trial registration: LUNG-SAFE is registered with ClinicalTrials.gov, NCT02010073publishersversionPeer reviewe

DIGITAL GAIN ERROR CORRECTION TECHNIQUE FOR 8-BIT PIPELINE ADC

An analog-to-digital converter (ADC) is a link between the analog and digital domains and plays a vital role in modern mixed signal processing systems. There are several architectures, for example flash ADCs, pipeline ADCs, sigma delta ADCs,successive approximation (SAR) ADCs and time interleaved ADCs. Among the various architectures, the pipeline ADC offers a favorable trade-off between speed,power consumption, resolution, and design effort. The commonly used applications of pipeline ADCs include high quality video systems, radio base stations,Ethernet, cable modems and high performance digital communication systems.Unfortunately, static errors like comparators offset errors, capacitors mismatch errors and gain errors degrade the performance of the pipeline ADC. Hence, there is need for accuracy enhancement techniques. The conventional way to overcome these mentioned errors is to calibrate the pipeline ADC after fabrication, the so-called post fabrication calibration techniques. But environmental changes like temperature and device aging necessitates the recalibration after regular intervals of time, resulting in a loss of time and money. A lot of effort can be saved if the digital outputs of the pipeline ADC can be used for the estimation and correctionof these errors, further classified as foreground and background techniques. In this thesis work, an algorithm is proposed that can estimate 10% inter stage gain errors in pipeline ADC without any need for a special calibration signal. The efficiency of the proposed algorithm is investigated on an 8-bit pipeline ADC architecture.The first seven stages are implemented using the 1.5-bit/stage architecture whilethe last stage is a one-bit flash ADC. The ADC and error correction algorithms simulated in Matlab and the signal to noise and distortion ratio (SNDR) is calculated to evaluate its efficiency

EC-Crypto: Highly Efficient Area-Delay Optimized Elliptic Curve Cryptography Processor

Elliptic Curve Cryptography (ECC) based security protocols require much shorter key space which makes ECC the most suitable option for resource-limited devices as compared to the other public key cryptography (PKC) schemes. This paper presents a highly efficient area-delay optimized ECC crypto processor over the general prime field ( $\mathbb {F}_{p}$ ). It is structured on a new novel finite field multiplier (FFM) where several optimization techniques have been incorporated to shorten the latency and hardware resource consumption. The proposed FFM architecture is embedded with a finite field adder/subtractor (FFAS) unit which is utilized to perform FFAS operations instead of deploying a dedicated unit. The Common Z (Co-Z) coordinates with the Montgomery ladder method are used to compute point multiplication, a core operation in all ECC-based crypto protocols. The work also proposes an efficient scheduling strategy to execute low-level finite field arithmetic primitives with minimum latency on the employed finite field arithmetic units. Due to these techniques, the proposed ECC processor is optimized for hardware resources, latency, and throughput. It is captured in Verilog-HDL, synthesized, and implemented on Virtex-7, Kintex-7, and Virtex-6 FPGA platforms using Xilinx Vivado and ISE Design Suite tools. On the Virtex-7 FPGA platform, it computes a single 256-bit scalar multiplication primitive in $0.7~m\text{s}$ , consumes just 6.2K slices, and delivers a throughput of 1428 operations per second. The implementation results show that it is a highly efficient design outperforming the state-of-the-art by providing a better area-delay product and higher efficiency. Therefore, it has the potential to be deployed in many applications where both latency and resource requirements are critical

Laminar Graphene Oxide Membranes Towards Selective Ionic and Molecular Separations: Challenges and Progress

Resolution of resources and environmental crises requires an efficient separation technologies, consequently, scientists and engineers are working vigorously for ideal separation materials. Laminar graphene oxide (GO) is a two-dimensional (2D) material offers considerable interest in this field due to its single atomic layer thickness, good stability, chemical inertness, and variety of functional groups. Recently, GO have emerged as a novel membrane material for molecular and ionic separation of gases, solvent, water, and desalination applications. This tutorial review aims to discuss the various approaches used to control the stacking of GO-based membrane with emphasis of advantages and drawbacks associated with each approach. Further, attention will also be given to describe the recent progress in GO based membranes for ionic and molecular separations. Meanwhile, challenges and opportunities will also be discussed in detail. We hope this review expected to provide a compact source of information that will be of great interest to chemists, material scientists, physicists, and engineers working or planning to work in GO based membranes for separation applications

Efficient soft core multiplier for post quantum digital signatures

Multiplication is a core operation in various applications such as cryptography and machine learning. Dedicated DSP blocks are provided by FPGA vendors for multiplication. However, these DSP blocks are limited in number and their location on FPGA is fixed, resulting in routing delays that affects the performance for small size multipliers. In this paper, a high performance and resource efficient 5 × 5 multiplier is presented that utilizes lookup tables (LUTs) and fast carry chain of the FPGA. The proposed multiplier offers 30% reduction in LUTs compared to Vivado DSP-less inferred multiplier at the cost of a slight increase in critical path delay (CPD). The proposed multiplier requires lesser power consumption and has better area delay product (ADP) and power-delay product (PDP) metrics. Based on the proposed multiplier, a finite field multiplier is developed for post quantum digital signatures such as QR-UOV, MAYO and MQOM. The matrix-vector architecture is the core operation in multivariate digital signatures and integration of our finite field multiplier in a matrix-vector architecture shows that area is almost halved compared to state-of-the-art

Modified Kenalog Protocol for Perianal Fissures- A Quasi Experimental Trial

Objective: To ascertain the role of triamcinolone injection at the base of an anal fissure and its effect on healing and pain relief. Methodology: A quasi-experimental study was conducted from November 2021 to February 2022. Under aseptic measures, a 1ml Triamcinolone 40mg/ml injection was administered at the base of the anal fissure using a 1cc insulin syringe. This was injected in four positions around the base of the fissure. Patients were followed for one week to assess pain relief and improvement in quality of life. Patients were assessed for quality of life improvement and satisfaction with treatment. Patients were offered lateral internal sphincterotomy at the end of one week and again on follow up after two weeks given they were not satisfied with pain relief or symptom recurrence occurred. Results: Twenty five patients were enrolled and analysed. All fissures were seen to have a red inflamed base at enrollment. At one week after treatment, a paler base with less signs of inflammation was observed. Patients reported a mean 70% improvement in their symptoms. A mean change of 16.45 points was seen in Brief Pain Inventory scores at one-week follow up. 25% underwent a lateral internal sphincterotomy. The number needed to treat was 2.5. 5 patients were lost to follow-up after the initial one week follow-up. Conclusion: Injection of Triamcinolone at the base of an anal fissure may have a role as an adjunct to standard management in treatment. It has been shown to decrease pain and enhance healing of the fissure thus decreasing the need for surgical intervention